Instructor: Brian T. Davis
btdavis@mtu.edu
Office Hrs : TBD
Office Rm : 729 EERC
Office Ph# : 487-2256
7th Floor Mailbox # : 40
| ECE 5772 Course Meeting Times | ||||
|---|---|---|---|---|
| Day | Time | Room | Type | Instructor |
| MON | 9:05-9:55am | 218 EERC | LEC | Prof. Davis |
| WED | 9:05-9:55am | 218 EERC | LEC | Prof. Davis |
| FRI | 9:05-9:55am | 218 EERC | LEC | Prof. Davis |
|
Class cancelations / rescheduling Fri Sept. 30th - Conference Travel |
||||
| Date Subject to change |
Reference | Chapter, Pages, Specifics |
|---|---|---|
| Wed Sept 7th | [Culler98] | Chapter 1 |
| [MPR96] | "Architects look to processors of future." Gordon Bell, Richard Sites, William Dally, David Ditzel, and Yale Patt. Microprocessor Report, vol. 10, no. 10, pp. 18-24, August 1996. | |
| [Culler98] | Chapter 5 | |
| [Stenstrom90] | "A Survey of Cache Coherence Schemes for MultiProcessors." Per Stenstrom. IEEE Computer, June 1990, pp. 12-24. | |
| [Hammond97] | "A Single-Chip Multiprocessor." Lance Hammond, Basem A.Nayfeh, Kunle Olukotun. IEEE Computer, September 1997, pp. 79-85. | |
| [Culler98] | Chapter 6 | |
| [Lilja93] | Cache Coherence in Large-Scale Shared-Memory Multiprocessors: Issues and Comparisons
| |
| [Becker95] |
BEOWULF: A PARALLEL WORKSTATION FOR SCIENTIFIC COMPUTATION
Donald J. Becker, Thomas Sterling, Daniel Savarese, John E. Dorband, Udaya A. Ranawak, Charles V. Packer. Proceedings, International Conference on Parallel Processing, 1995. | |
| [Culler98] | Chapter 7 | |
| Reschke96 | "A Design Study of Alternative Network Topologies for the Beowulf Parallel Architecture" | |
| [Culler98] | Chapter 10 |