ECE 5900_04 - Spring Term 2001 Hompage

Office Hrs : M 2-3pm ; W 2-3pm ; Th 1-3pm ; or by Appt.
Office Rm : 711 EERC
Office Ph# : 487-2256
Mailbox Rm : 121 EERC

ECE 5900_04 Course Meeting Times
Day	Time	Room	Type	Instructor
MON	1:05-1:55pm	226 EERC	LEC	Prof. Davis
WED	1:05-1:55pm	226 EERC	LEC	Prof. Davis
FRI	1:05-1:55pm	226 EERC	REC	Prof. Davis
Known Class cancelations 1/15 - MLK Day 2/9 - Winter Carny
Known Class reschedulings ( 1pm Fri 2/2 Rm226 ) --> ( 3pm Thur 2/1 Rm316 )

ECE 5900 General Information

ECE 5900 Syllabus
- Midterm Exam - 20%
  Date : 3/16/01
- Final Exam - 20%
- Programming Assignments - 35%
- Homework - 10%
- Class participation - 15%
Lecture Notes at the time of exam # 1.
Lecture Notes at the time of exam # 2.
Required Text : Computer Architecture: A Quantitative Approach. Hennessy and Patterson.(second edition) Morgan Kaufmann 1995.

All Dates are preiliminary and subject to change.

All lab reports should conform to the lab guidelines .

Lab #1 : Introduction to the SimpleScalar architectural simulation toolset
Assigned : 1/22/01
Due : 1/29/01
Lab #2 : Using SimpleScalar 3.0 for Architectural Analysis
Assigned : 2/1/01
Due : 2/15/01
Lab #3 : Adding a SRAM simulation engine to sim-outorder
Assigned : 3/14/01
Due : 3/30/01
Lab #4 : Adding a parameterized DRAM simulation engine to sim-outorder

SimpleScalar 3.0 Source code repository
Sample SS3.0 PISA (big endian) binaries from various places including : SPEC95, SPEC00, MediaBench, McCalpin, etc..
or access them from the directory
/usr/dept/faculty/btdavis/ss3.0_pisa_big_bin
Sample input sets for common benchmarks from various places including : SPEC95, SPEC00, MediaBench, etc..
or access them from the drirectory
/usr/dept/faculty/btdavis/benchData

All Dates are preiliminary and subject to change.

Readings from Chapters 4-6 of Hennessy & Patterson
- Chapter 4.1-4.4 by 1/22/00
- Chapter 4.5-4.11 by 2/1

"Architects look to processors of future." Gordon Bell, Richard Sites, William Dally, David Ditzel, and Yale Patt. Microprocessor Report, vol. 10, no. 10, pp. 18-24, August 1996.

"The microarchitecture of superscalar processors." Jim Smith and Guri Sohi. Proceedings of the IEEE, December 1995.

"Hitting the Memory Wall: Implications of the Obvious." Wm. A. Wulf and Sally A. McKee. Computer Architecture News, 23(1):20-24, March 1995.

"The slammin, jammin, DRAM scramble." Brian Dipert. EDN, pp. 68-82, January 2000.