Computer Architecture & Design
EET 3141 - Fall Term 2007 Hompage

Office Hrs : Posted on office door
Office Rm : 415 EERC
Office Ph# : 487-2256

lab

EET 3141 Course Meeting Times
Day	Time	Room	Type	Instructor
MON	1:05-1:55pm	314 EERC	LEC	Prof. Davis
WED	1:05-1:55pm	314 EERC	LEC	Prof. Davis
FRI	1:05-1:55pm	314 EERC	LEC	Prof. Davis
Tue	11:05am-1:55pm	427 EERC	LAB	Prof. Davis
Class cancelations / rescheduling Week of 9/3-7 NO LABS

EET 3141 General Information

EET3141 Syllabus
- Midterm Exam #1 :
  Tentative Date : Tuesday 10/16 @ 6-8pm
- Midterm Exam #2 :
  Tentative Date : Thursday 11/15 @ 6-8pm
- Final Exam : Tentative Date : Wednesday 12/19 @ 12:45-2:45
Required Text :
Essentials of Computer Architecture , Douglas E. Comer, Prentice Hall.
ISBN-13: 9780131491793; Published: 08/13/2004; Copyright 2005.
Textbook resource website
Resource Texts :

Homework # 1 : Processor Types, Performance equation, Process technology & FPGA
Due : 9/28
Homework # 2 : Processor optimizations, ISA Features, Performance calculations
Due : 10/16

Lab # 1 : Introduction to the Quartus II Software
Performed : 9/11
Report Due : 9/18
Lab # 2 : Combinational Logic in Quartus II
Performed : 9/18
Report Due : 10/2
Lab # 3 : Implementing an Adder/Subtractor in Quartus II
Performed : 9/25
Report Due : 10/9
Lab # 4 : Adding pipeline registers to a Adder/Subtractor
Performed : 10/9
Report Due : 10/6
Lab # 5 : Transition from Digital Circuits to Microprocessor
VHDL Code for Enhanced processor
Performed : 10/23
Report Due : 10/30
Lab # 6 : Introduction to SOPC builder
Performed : 10/30
Report Due : 11/6
Lab # 7 : Nios II IDE
Performed : 11/6 & 11/13
Report Due : 11/29
Lab # 8 : Polled and Interrupt I/O Using the Nios 2 Processor
Will be largely based upon : Altera Computer Organization - Lab # 4
Code for Part2 can be found at : Lab 8 source code
Performed : 12/6 & 12/13
Report Due : 12/17

Many of the labs reference material available from Altera Tutorials and Lab Exercises

All labs should be submitted in a format consistant with the Lab Policies and Guidelines.

Date Subject to change	Reference	Chapter, Pages, Specifics
Wed Sept. 5	Comer05	Preface & Chapter 1
Wed Sept 12	Comer05	Chapter 4
	Architecture of FPGAs and CPLDs: A Tutorial," Stephen Brown and Jonathan Rose	www-old.ti.informatik.uni-bonn.de/html/fpga_cpld_tut.pdf klabs.org/richcontent/Tutorial/fpga/Toronto_tutorial.pdf
Wed Sept 19	Comer05	Chapter 18

btdavis (at) mtu (dot) edu