btdavis@acm.org

This Page is Always Under Construction, so if you locate any errors please report them to me at the email listed. Thank you.

Critical Documents

Employment/Educational History

As of the most recent time this webpage was updated, I am an Assistant Professor at Michigan Technological University working in the Electrical and Computer Engineering Department .

Current Research Projects and Topics

NSF CAREER
National Science Foundation
Award No. CCF - 0133777
Funded 7/1/2002 - 6/30/2007 		The gap between microprocessor and memory system cycle times has been increasing over the past 15 years. In practice, because of the many levels in the memory hierarchy and interconnection busses between the processor and DRAM, a primary memory access may take 200 processor clock cycles from request to response; more than 50% of this latency is due to the memory hierarchy and interconnect. This research will focus upon the reduction of this fraction by novel interconnect techniques and increased focus on the DRAM controller management policies. As the amount of state present in DRAM devices increases, the available set of memory controller policy decisions also increases; this increased flexibility allows an intelligent memory controller to optimize controller policies to achieve increased performance. This research will examine the potential for improved performance when the memory controller changes from a static control policy to a dynamic control scheme. This impact will be simulated over a variety of interconnection topologies from the current NorthBridge to a CMP architecture with multiple DRAM busses.

Project Website

WESN Creation of an Environmental Monitoring system for the Michigan Tech Ski Trails.

Two M.S.E.E students : Divyakant Gupta & Gaurav Kulkarni

Research Groups, present & past

Past Research Topics

Memory System Hierarchies for High Speed Microprocessors Microprocessors are getting faster at a rate which approaches a doubling in speed and throughput every two years. This rate of speedup is dramatically faster than the rate of speedup which is being observed in Dynamic Ram (DRAM), the primary memory storage device used in todays computers and workstations. Therefore it is the modern computer architect's job to design a memory hierarchy or subsystem which despite the limitations of the basic circuit which makes up the memory (DRAM) can satisfy the requests which are made by the high speed microprocessors of today and the future. Many approaches to this problem have been examined, ranging from multilevel-caching to interleaved memory banks to the new DRAM technologies such as pipelined DRAM, synchronous DRAM, extended-data-out-DRAM and RAMBUS. The task of this project is to generate more systematic methods for designing memory hierarchies and in completion to generate a memory hierarchy for the PUMA high speed microprocessor.
Hardware Description Languages (HDL) My concentration in this area was with the Verilog HDL. The intent of this research was to provide a basis for inspection of new functionalities within Verilog before they are implimented in commercial compilers and simulators. To this end, I have constructed a preprocessor for the Verilog HDL which can accept non-standard Verilog source code and convert it to standard (Cadence Verilog-XL compatible) Verilog source code.
btdavis@acm.org