Signaling Through Interconnects
Where/When: EERC226, 1:05pm, 4/10/2003
The signal’s propagation speed through the integrated circuits has gradually improved over the past decade as a result of devices becoming smaller and faster. For the time to come, the typical gate length of a MOSFET has been projected to be 0.1 um and 0.05 um in 2006 and 2012 respectively. In the mean time, the device density in chips will increase with an estimate of more than 50 millions devices on a single chip. Interconnects, which are connecting devices will decrease in size and increase in density due to this tendency. The scaling of interconnections poses several serious metallization problems including the increase in interconnection delay and the circuit’s reliability. All estimates project that at gate lengths of about 0.13 um (gate length of transistors used in Pentium IV) and below, the interconnections will dominate the communication speed through the circuits. Thus, there is a large effort in research for materials and technologies by which the impact induced by the interconnects can be minimized.
This talk will discuss the basic concepts of IC interconnects; the modern trend in scaling of high speed VLSI devices, the impact of interconnects on overall chip delay and the probable ways of reducing these propagation delays.